Qualcomm, Bangalore Design Center, India
In Summers of 2019 I was with the Memory Design Team at Qualcomm Bangalore where I worked on the detection of Electromigration prone structures from layouts and reviewed the read/write assist and current/voltage sense amplifier ciruits. I was offered pre-placement job opportunity based on my performance.
Pix Moving, Guiyang, China
In December 2018, I intered as an Car Electronics and Control Engineer at Pix Moving. I developed a CAN based system of braking, steering and accelerator unit on ARM microcontrollers. Hacked BAIC EV car’s ultrasonic system for parking assistance and assisted the team in debugging the pix Robo-vehicle motor driver units.
Fujita Lab, VDEC, The University of Tokyo, Japan
In Summers of 2018, I was VDEC intern with Prof. Masahiro Fujita, I worked on CAD tool development for partial logic synthesis using discrete valued DNN and And Inverted Graphs (AIGs). Moreover I implemented existing discrete DNN algorithm on tensorflow, along with QBF based architecture verification.
VLSI Summer School, AVLSI Lab, IIT Kharagpur, India
In Summers of 2017, I attended two months long VLSI Summer School by Prof. Mrigank Sharad. I worked on various design problems in analog and digital domains such as Opamp design, low noise amplifier for bio-medical front-end and RTL design with implementation in LTSPice, Cadence Virtuoso and XIlinx ISE.
The group consists of a bunch of robotics enthusiasts working on the development of autonomous soccer-playing robots for participation in International Competitions like RoboCup and FIRA. Currently, I am the Student Advisor to the group with a focus on the Embedded Electronics team which is responsible for the design of FPGA based circuits involving communication with the base station and BLDC motor based control unit. During my third year, I led the team at Robocup 2018 at Nagoya, Japan (first Indian team at SSL Robocup). Planning to participate in next year Robocup 2020 at Bordeaux France.
The project was an extension of my training at VLSI Summer School IIT Kharagpur, guided by Prof. Mrigank Sharad, presently at Dep. of Engineering Entrepreneurship IIT Kharagpur prev. Dept of E&ECE, IIT Kharagpur. The aim of the project is to design a low power multi-bit adaptive SRAM topology-based analog PUF which variations generated from the mismatch in the current mirror structures considered as bitcell. The other contributors of the project include Dhruv Thapar and Nikhil Bhelave Dept. of EE, IIT Kharagpur.
Side Channel Analysis of Block Cipher GIFT
This project was my final year BTech project under Prof. Debdeep Mukhopadhyay, CSE IIT Kharagpur. The project includes implementation of block cipher GIFT on FPGA, followed by its side-channel analysis using power traces (CPA attack was used), and then looking for the vulnerability in the threshold implementation of the cipher. Sayandeep Saha (PhD Student), SEAL Lab, CSE IIT Kharagpur was my mentor in this project.
The group aims to develop an exoskeleton for the lower extremity of the human body consisting of actuators and feedback sensors, to impart a locomotive ability to the physically disabled people. For measuring the gait cycle collection of nodes consisting of IMU and RF module was developed. Advised by Prof D. K Pratihar and mentored by Abhishek Rudrapal (PhD Student) at Dep. ME IIT Kharagpur.